By Subi Kengeri
Consumers continue to demand smaller, faster and more energy-efficient electronic devices, driving the semiconductor industry to accelerate development of commercially viable chips on more advanced nodes. However, these new nodes don’t just appear by magic. It takes a great deal of careful planning to develop and deliver a process technology platform that offers competitiveness, differentiation, and manufacturability. THIS IS THE JOB OF MY TEAM AT GLOBALFOUNDRIES. It always has been difficult, but the transition to 20nm and beyond presents a host of new challenges, requiring a fundamentally new approach to technology architecture and definition.
Over the past few nodes, SoC designers have grown accustomed to a roughly 30% reduction in die cost from node to node. But 20nm is the first node on which foundries introduced true double-patterning lithography, which increases manufacturing costs, largely dependent on the target application. So there has to be something else to prompt customers to adopt this new node. For example, it is critical that a technology platform deliver SoC product value and designability, and has to be optimized for the customer’s target application. At 20nm, we really began looking at the product level value for customers, which we define in terms of the optimum combination of performance, power and cost (PPC), in addition to other customer care-abouts.
We took this to a whole new level with our recently launched 14nm-XM offering. Once we had optimized PPC for our 20nm planar SoC offering, we looked at what it means to incorporate 3D FinFETs on the next node. Going from planar to FinFET gives us a step jump in performance and power, but minimal benefit in die size because we chose to use the fully optimzed middle and backend of line from 20nm-LPM. The key was to architect 14nm-XM to ensure the performance and power advantages outweigh the lack of area improvement and to ease designability on the first generation FinFET offering. Leveraging the 20nm-LPM competitive density advantages and using the most optimal 3D fin structure, we expect to get back on the historical 60% to 70% SoC PPC improvement trajectory. We also expect to see a big benefit in time-to-volume (on a node to node basis) because we will leverage key technology modules and PDKs from 20nm-LPM, which we believe will allow our customers to design concurrently and accelerate our FinFET high volume ramp by about one year.
But one question I often get asked is, ‘Why do we call it a 14nm technology if it relies so much on 20nm?’ First of all, we are using a true 14nm-class FinFET as the front-end device, which qualifies it as a 14nm technology. But in reality the naming of nodes has become somewhat arbitrary over the past several nodes. A node used to be named based on the smallest transistor feature size, which was typically the channel length. But channel length scaling stopped at about 45nm, so the industry does not actually have a 28nm gate in a 28nm technology. Secondly, the point of moving to a new node is the delivery of value to the customer. They need to see a SoC level product value, which really translates to the PPC, and 14nm-XM offers a full node value. As long as customers see at least this level of value, they frankly don’t care what the technology is called or what is inside.
Now we need to find a way to deliver this same product level value at 10nm. The whole industry has quite a few challenges going to 10nm. FinFETs are scalable and will have a long life, but we will have already realized the performance and power value from the front-end device with 14nm-XM. We don’t expect extreme ultraviolet (EUV) lithography will be ready, at least not at the beginning of the node, which means we will have more layers that require multiple patterning and therefore significant cost increases. We will need to find other ways to provide performance and power benefits to deliver a total PPC to stay on the SoC value trajectory. We have been working on this and 7nm technologies for several years and we are very close to nailing down a competitive 10nm technology architecture. We are running 10nm devices in silicon and I am confident we will deliver the value our customers have come to expect.
For more detail on this topic, check out the recent interview with SemiMD’s Mark LaPedus, where we talk about FinFETs, EUV, and Moore’s Law.
Subramani “Subi” Kengeri is vice president of advanced technology architecture at GF.
This post also appeared on Chip Design Magazine