When journalists think about how semiconductor companies compare, we often drill down into gate lengths, mask layers, SRAM cell sizes, and other hardware-oriented metrics. It was only midway through my own career that I started to realize that intellectual property (IP) and other forms of design support were just as important to the success of both foundries and integrated device manufacturers (IDMs).
When GF announced its “pivot” in late August 2018, much of the public attention again went to the role of the transistors, and how resources could be redeployed into other than 7nm logic. And yes, spreading those efforts out over the 18 different technologies (and sub-variants) offered by GF has received a fair amount of understanding in the era of a slowing Moore’s Law.
What needs a bit more emphasis is the renewed push on intellectual property (IP), in part made possible by the pivot.
Mark Ireland, vice president of ecosystem partnerships GLOBALFOUNDRIES, said the 12LP (FinFET) process is a good example of redeploying IP resources. In its initial phase, GF’s 12LP process was used primarily for CPUs, GPUs, and similar high-performance products. Now, 12LP is going into a broader set of markets, including consumer, networking, 5G wireless, and artificial intelligence-machine learning (AI-ML). These often require different IP, notably multi-protocol SERDES, low-power memories, and high-speed memory interfaces.
“In consumer, digital video and set top boxes are moving into FinFETs. Consumer did not lead that (12LP) node, but now it is moving into FinFETs. We are seeing a much broader set of markets and a broader set of customers, and that has to be reflected in the focus of our IP partnerships,” Ireland said.
Artificial intelligence SoCs also need additional IP, including high-speed SERDES and low-power memories, he said.
High-Speed SERDES for 5G Base Stations
Similarly, the 5G wireless standard “has broadened the need to bring in some high-speed SERDES IP that will be used in 5G base stations and elsewhere. That is the kind of IP that our customers need to be successful in these markets,” he said, noting that wireless customers can opt for the 22FDX fully-depleted silicon-on-insulator, 12LP FinFET, or other processes, depending on their application needs.
GF and Rambus announced 28-Gbps and 32-Gbps SERDES for the 22FDX process, and just prior to the Design Automation Conference, GF and Synopsys said they were readying a 25-Gbps SERDES on the 12LP process. “While it has broader market applications, this is the kind of IP that is very critical for 5G base stations,” Ireland said.
Also, GF and Analog Bits recently struck a deal to bring Analog Bits’ analog and mixed-signal IP design kits to the 12LP technology, including low-power phase-lock loop (PLLs) with spread spectrum clock generation (SSCG), process, voltage, and temperature (PVT) sensor IP, and others.
“We are developing deeper partnerships across a broader set of markets to meet the need for more IP. We are driving the process, and there is no lack of opportunity. The challenge in front of GF is to get the highest quality IP in place on time and on schedule,” Ireland said.
A Radio On Every Chip
Subi Kengeri, vice president of client solutions at GLOBALFOUNDRIES, said rather than rely on brute scaling, more IC design teams are pursuing complex designs with RF and mixed-signal either using FD-SOI or a traditional heterogenous integration approach. For complex RF and Analog SoCs, Kengeri said “the IP is the carrier of technology differentiation to the SoC. It is how designers extract the differentiated value of the technology. So it becomes important that the IP is fully optimized and has the highest quality.”
GF has a strong track record in RF technology, and keeping investments strong in RF IP is part of the post-pivot strategy. “Communication is becoming more important than ever, and every chip will have a radio in it. RF is very complex and the skill set is limited throughout the industry. We are no. 1 in the RF world, and by having invested in that IP, design services and RF reference blocks, we are well positioned to give our customers faster time-to-market and lower costs, with least risk. Think RF. Think GF.”
Tracking IP Readiness
John Kent, vice president of foundry IP and customer engineering, said a chip design may require 20 or more different IP titles. “We track IP readiness, and by that I mean when a customer wants to do a design, do we have all the IP necessary?” Kent said. That readiness metric is a “critical indicator that we are able to service a customer.” Another important metric, Kent said, is first-time-right, making sure all of the IP’s DC parametrics are accurate.
“Our on-the-ground experience with new customers tells us where we are world class, and where we have work to do. The biggest challenge we have as a team is balancing our resources as we redeploy off of seven nanometers, using some of the experience the team developed at 7nm on other platforms,” he said.
Kent said other GF technology platforms have received more attention, including an ongoing focus on improving the PDKs (product development kits). “Our PDK learning has been a work in progress over the last ten years as we have learned to execute in a timely fashion. With that process, and then the pivot, we were able to shift the primary PDK development focus from just FDX and FinFET to some of the other 18 families that GF provides its customers, redeploying much of our PDK resources across those technologies,” Kent said.
For the 22FDX foundational IP, GF has relied primarily – but not exclusively – on Invecas, which includes former members of the IBM memory IP team. Kent said of Invecas, “It’s a great team and produces great products.”
“Our base 22FDX foundation IP is from Invecas, and recently we have expanded our ecosystem to include automotive IP from Synopsys. It is our intention to work with multiple suppliers,” Ireland said. The deal with Synopsys includes foundation IP as well as analog and interface IP targeted to automotive applications such as ADAS, powertrain, 5G, and radar.
Foundation IP Can Be Complicated
Foundational IP, or FIP, can range from simple to moderate complexity. General purpose IO with multiple voltages can involve several different metal stacks and can be quite a complex design. “Typically when we release a library there are several thousand individual library cells composed within the FIP,” Kent said.
Memories, including Static RAMs, ROM, flash, and more recently MRAM, are included as FIP because, like I/O, they are foundational to a design. But memory IP is complicated, with sophisticated signaling problems and error correction.
So-called complex IP often has a significant amount of analog and mixed-signal content. A 32-Gbps SERDES can have many digital-mode functions, as well as complex mixed-signal to support signal and power parameters.
GF has been working with Everspin to develop new IP supporting the embedded MRAM for both the 22FDX and FinFET-based processes. Kent said MRAM has advantages over flash, including sub-nanosecond write times, (compared to milliseconds for flash), and very strong failure resistance. “We are developing new IP (to support MRAM), including classes of performance which mimic SRAM,” Kent said.
Automotive applications are a prime target for MRAM. “The automobile of the future will be covered with sensors, and everything has to run safely. MRAM is being contemplated because the ICs have to run longer in a car than, say, a computer is expected to last,” Kent said.