Packaging has emerged as one of the semiconductor industry’s most potent forms of innovation. As classical (geometric) scaling has become more difficult, various “equivalent scaling” innovations have stepped up to the plate, notably 193nm immersion lithography, strained silicon, high-k/metal gate, finFETs, fully depleted SOI, and vertical NAND.
Now it is packaging’s turn, and that puts the spotlight on experts such as Dave McCann, the vice president of packaging research and development at GLOBALFOUNDRIES.
In an interview at his office in Malta, N.Y., McCann said more customers are turning to packaging innovations. “In all application spaces, customers are, more than ever before, integrating multiple chips in one package to address scaling limitations,” he said.
For high-bandwidth applications such as servers and networking, McCann said GF is the only foundry to have 32nm TSVs in high-volume production.
“We are getting a lot of customer requests for 2.5D design, which take advantage of our experience in ASICs plus memory and high-speed Serdes. Most of these are on silicon interposers, on which we create high density traces to interconnect the ASIC and memory, so that customers achieve very high bandwidth products.”
RF and IoT innovations are also driven by multi-chip applications, utilizing chips from different GF fabs and nodes. This enables use of chips at the most cost efficient node rather than forcing integration and suboptimum costs, he added.
One intriguing R&D thrust for some RF and IoT applications is to use glass substrates, instead of silicon, which can be too lossy. “We believe we can create very dense interconnects, and get rid of all of the passives, using through-glass vias. Products could become much thinner,” McCann said.
Photonics is another important area. The goal is to bring photonic signals directly to the module, instead of stopping at the board or backplane.
For upper-end mobile and other markets, McCann said “wafer-level fan out is a terrific technology first for enabling more IO. Later we will see it used also for integrating multiple chips, starting with the memory and apps processor.” High density fan-out applications will cost more than the low cost substrate-based packages they will replace, however.
Thin glass and FO-WLP allow multiple chips to be placed very close together, providing for a much smaller footprint, thinner profile, and higher performance. The profile is thinner because the laminate substrate is eliminated. And McCann noted these technologies are “particularly interesting for RF and IoT, because of the low loss for high frequency signals.”
“The lowest cost WLFO supply chain will utilize OSATs for what they do best. We do not want to do what an OSAT can do just as well, or better. Especially in the mainstream technology areas, OSATs can offer their solutions to many customers, more cheaply than we could internally,” McCann said. He added that this gives customers the flexibility to use the supply chain they want to use.
“The combination of GF with IBM’s Microelectronics division brings new opportunities, including high-density stacking applications. Being the only Foundry with HVM experience on high-density 3D TSV in logic, we bring credibility to the marketplace,” McCann said. In addition to TSV’s in 3D, GF designs and develops 2.5D silicon interposer products in-house for volume manufacturing at OSATs, “providing the best combination of design skills with a low-cost production path.”
“GF is also working on low-cost alternative memory technologies that will scale with new silicon nodes at no added layer cost and technologies for use in multiple product technologies,” McCann said.
Industry analysts said they are keeping a close eye on the foundry’s packaging skills.
Dick James, senior fellow at ChipWorks (Ottawa) said GF has an opportunity to further leverage the through-silicon via and interposer technology developed within IBM Microelectronics over the last decade. James noted that the recently released executive summary of the International Technology Roadmap for Semiconductors (ITRS) emphasized the need to integrate heterogeneous ICs in system-in-package solutions. Putting together high-bandwidth memory with graphics processors is a particularly important area going forward, James said, one that will take advantage of the interposer experience at the GF Fishkill, N.Y. fab. McCann added that this also will build on GF’s expertise in large thin die stacking.
Jan Vardaman, president of the Austin, Texas-based packaging consultancy TechSearch International, said her firm is seeing increased uses of silicon interposers for high performance applications. “The use of a silicon interposer allows the use of a heat spreader on the top to help remove heat,” she noted.
The use of wafer-level fanout packaging is also bringing a lot of infrastructure changes, Vardaman said, starting with IC/package co-design.
Thus far, most application processors had been using a laminate substrate with flip chip interconnects. “With fan out WLP there is no need for a traditional laminate substrate with underfill. There are just a lot of infrastructure changes. All packaging can take place at the foundry, or at an OSAT which has a non-traditional OSAT assembly line,” Vardaman said.
TechSearch is seeing a rapid adoption of FO-WLP beyond its widespread use in baseband processors, to RF transceivers and switches, power management integrated circuits (PMICs), automotive radar modules, near field communications (NFC), audio CODECs, security devices, and microcontrollers.
It’s no wonder, then, that customers are beating a path to Dave McCann’s office. McCann said “the number of customer engagements is multiplying,” attracted by the mix of OSAT partners and internally developed technologies.
“GF does not ever plan to be an OSAT. But where the OSAT is not investing, where we can develop unique capabilities internally and gain a differentiating advantage, then we will partner with an OSAT to ramp that solution into production,” McCann said.