Foundry Files Blog

Innovation in Design Rules Verification Keeps Scaling on Track

  • By: Communications
  • August 28, 2012
  • Category: Technology

By Mojy Chian

There is an interesting dynamic that occurs in the semiconductor industry when we talk about process evolution, roadmaps and generally attempt to peer into the future. First, we routinely scare ourselves by declaring that scaling can’t continue and that Moore’s Law is dead (a declaration that has happened more often than the famously exaggerated rumors of Mark Twain’s death). Then, we unfailingly impress ourselves by coming up with solutions and workarounds to the show-stopping challenge of the day. Indeed, there has been a remarkable and consistent track record of innovation to keep things on track, even when it appears the end is surely upon us.

But this time we are really serious – at 20nm, the end is near! Ok, maybe not THE end, but for sure there are some obvious things that need to change if we are to keep our record of continuous technical conquest intact. And, as with most things in this era, collaboration is the key.

Mojy Chian explains the role DFM has in keeping scaling on track.

Sure there are lots of really innovative approaches and exotic technologies being bandied about that hold the potential to keep Moore’s Law chugging along well into the future. But ironically, it’s something of an ‘old’ technology that holds significant potential to address the current issues. Design for manufacturing (DFM) has been around for a long time, most typically as a design-enabling tool delivered by EDA companies to help IC designers understand and deal with manufacturers’ geometrical design rules.  This obviously requires close interaction with the EDA people and the foundries so that design rules are accurate and practical. Literally, these are tools that guide designers with a set of geometrical constraints, necessary to guarantee yield, defined over polygonal shapes and edges in the layout. Traditionally, these design rules are binary – this works, this does not.

But something funny happened on our way past 28nm. The Y word – yield – started becoming one of the, if not the, most important factor in successful IC design. This is because of the intrinsic relationship between yield and the complexity of physical design (and the associated challenges of process-related effects).

In the past, a designer only had two primary options for identifying DFM issues: run accurate but computationally intensive simulations based on numerical algorithms, or rely on metrology measurements directly from the fab. Attempts have been made to improve upon standard DRC with additional rules, but these approaches have had mixed success. For example, some have proposed the use of restrictive design rules that only allow highly regular structures for layout, avoiding problematic two-dimensional geometries altogether. The potential drawback is that designers cannot effectively optimize their circuits to meet application requirements with overly constrained design rules.

So the manufacturers got back together with the EDA suppliers and thought about how to solve the problem. “We need to build on what we have achieved with DRC,” we agreed. “We need more.” So in our infinite wisdom, we came up with something called DRC+. The lack of creativity in the name, however, belies the innovation behind it, which is backed by several patents and reinforces the fact that GLOBALFOUNDRIES innovates in ways beyond just manufacturing process technology.

The concept we are moving towards is the reduction in the number of trade-off decisions a designer needs to make. By providing a tool that will notify the user if a forbidden shape has been used, the designer can be guided more efficiently. In addition, things need to be visually intuitive –  a picture is worth of a thousand words, even in IC design. Such a solution requires tight collaboration between the foundry, which supplies a library of yield critical patterns; EDA providers, which supply ultra-fast pattern-matching tools; and the IC design community itself which provides valuable input on design methodologies and real-world needs.

Pattern-based methodology takes hold

In a nutshell. DFM and design rule checking need to move to a pattern-based approach to provide more visibility into variability issues. Traditional DRC is shape and edge proximity based.  On top of that, we need 2D shape-based pattern-matching physical verification.

As a result, our DRC+ takes a different approach than earlier generations of DRC. Instead of restricting the flexibility of designers, the technique augments standard DRC by applying rapid two-dimensional shape-based pattern matching to identify problematic configurations that could be difficult to manufacture.

Our DRC+ platform includes a silicon verified library of “bad” patterns in a database which can be identified quickly in layout, allowing the designer to fix them. This is an on-going incremental process rather than just occurring at the end of the complete design cycle.

Thus, pattern matching with DRC+ introduces process-awareness earlier in the design process, a concept that is at the basis of the collaborative DFM platform from GF.

Two rule-based flows are also part of our DFM platform. The first is yield analysis and scoring, in the form of an equation-based tool to help designers quickly analyze their design for usage of recommended rules, and prioritize fixes for the highest impact violations. The second is an automated yield enhancement “layout-fix” application, which applies recommendations without impacting overall design area.

The net result is improved variability management without sacrifices in design performance or significant impact on design productivity (DRC+ is over 10,000 times faster than printability simulation, and its detection and fixing adds very little to the overall routing runtime).

DFM is something of a broad catch-all term for a number of steps and issues involved ensuring a complex IC design can be manufactured and done in a way that is cost-effective and timely. Design rule checking is just one aspect of it, but a critical one for sure. We are proud of the innovation GF continues to demonstrate in many areas, including design enablement technologies like our DRC+. In future posts I’ll explore other ideas for improving how manufacturing issues can be brought more tightly into the design process, including a concept we call Design Enabled Manufacturing (DEM). Stay tuned.

Mojy Chian is senior vice president, design enablement at GF. He is responsible for global design enablement, services, and solutions and is the primary technical customer interface for the company. 

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