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Foundry Files Blog

GF’s 12LP Process: Behind the Covers

A couple of nanometers counts for a lot in today’s semiconductor industry. In an earlier era, foundries would offer a half-node by performing a “litho shrink,” without many changes other than pushing the mask and stepper configuration.

GLOBALFOUNDRIES move to a 12LP process is much the opposite, using the same patterning as on the still-going-strong 14LPP platform but with many subtle changes to the process and standard cell library to achieve improvements in performance, power consumption, and area (PPA). First announced in September 2017, with public support from Advanced Micro Devices (AMD), the details of the process changes came to light in a presentation at the 2018 Symposium on VLSI Technology, held in Honolulu in late June.

On the business side, GF has prepared automotive and RF/analog modules to better support those markets with its 12LP offering. The 12LP process got a major boost last autumn when AMD said it would quickly move major product lines to the 12LP process. Then a mobile customer began using 12LP for its application processors.

Erin Lavigne, deputy director of leading edge FinFET offering management at GF, said “most of the customer interest is in 12LP going forward.” Customers that are designing new ICs go for the higher transistor density, power and performance gains, with cost savings coming from smaller die sizes.

Because the tool set is virtually the same, the manufacturing corridor can be “flexed” for either 14LPP or 12LP production. “Our capacity is fungible,” Lavigne said. “While AMD is a key strategic customer of ours, Fab 8 is not full with just AMD. We can support all of our customers, while continuing to support AMD’s needs. Besides our two lead customers, the pipeline has exploded in fast followers in consumer, AI, automotive, and industrial segments,” Lavigne said.

Hsien-Ching Lo, a GF technology development deputy director, said in one important area — the back end of the line (BEOL) — GF has taken a different approach from its foundry competitors. While other foundries have reduced the M2 pitch to achieve die size reductions, the GF 12LP employs the same 64nm M2 pitch as its 14LPP process. That strategy allows customers to gain in performance, power, and area (PPA) “while minimizing design rework.”

Supporting evidence for that statement came at the VLSI conference in Hawaii. A Samsung Foundry presentation of its 11LP process described an ability to use either a 9T or 6.75 track library. The 6.75T library, however, requires using a 48nm pitch M2, compared with the 64nm M2 pitch of its 14nm process. TSMC has taken a similar tack, changing the M2 pitch for its 12nm offering, which is a follow-on to its 16nm process.

Lo said moving to a different M2 pitch is a design rule change that requires much more design rework than the GF strategy of supporting its 7.5 track library with the same M2 pitch. “It is much easier for our customers to migrate from 14 to 12. They can get a performance and area benefit, with a very small design migration,” he said.

While GF continues to support the 14LPP 9T library for 12LP designs, Lavigne said the 7.5-track library “offers the most bang for the buck” in both die size reduction and higher performance. “There is some redesign for customers to use that library. They can choose how much redesign they want to do to extend the platform.”

Compared with the GF 14LPP process, the 12LP with performance elements delivers a 15 percent faster ring oscillator AC performance, 16 percent less total power for the 12LP (with the 7.5T standard cell library) at equivalent speed, and 12 percent logic area scaling. Notably, the 12LP SRAMs benefit from a 30 percent leakage reduction at the same read current.

GF’s 12LP are improvement. Source: H.C. Lo presentation at the Symposia on VLSI Technology and Circuits

Lo took the stage at the VLSI symposium to describe the five process element modifications in the 12LP process.

The fin profile was improved to a taller, thinner fin, improving the drive current and short channel control. Also, the fin surface roughness was reduced, resulting in a carrier mobility increase of 6 percent for the NFET and 9 percent for the PFET.

To improve the PFET performance without increasing leakage, the source/drain cavity profile was modified, moving from a bowl-shaped cavity in the 14LPP process to a deeper cavity in the 12LP process. The enlarged cavity is needed to improve the strain on the channel, delivering more embedded silicon germanium (eSiGe) but without the penalty of higher leakage.

Thirdly, the eSiGe was optimized to improve pattern loading effects, with a 4 percent improvement to the 40-fin devices and a 5 percent improvement to the single diffusion break (SDB) devices.

PEFT eSiGe Optimization. Source: H.C. Lo presentation at the Symposia on VLSI Technology and Circuits

Fourthly, the NFET doping density was increased. By optimizing the silicon-phosphorus epitaxial process, the source-drain resistance was improved by roughly 6 percent, Lo said.

Contact resistance is a major concern at leading-edge design rules. GF’s Advanced Technology Development team exercised dual optimizations to reduce the contact resistance. The trench contact profile was improved by enlarging the bottom contact size. “We wanted to enlarge the contact area and the bottom CD (critical dimension), but without a penalty in terms of TDDB (time dependent dielectric breakdown). Typically, with an increase in the contact CD, the space between contact to polysilicon gate becomes smaller. Then you can see a degradation in the dielectric breakdown,” Lo said in an interview at the VLSI symposium.

Also, the doping profile under the trench contact was optimized to reduce the contact barrier height. And the silicide resistance was improved by “some interface engineering,” he said.

On the surface of it, going from 14nm to 12nm may not seem to be such a big deal. But scratch the surface, and a lot of engineering work went into delivering a compelling technology.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF's Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

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