Foundry Files Blog

FX-14™ Methodology: A Formula for First-Time-Right Success

  • By: Communications
  • November 28, 2016
  • Category: Markets

GLOBALFOUNDRIES’ VP of the ASIC product line shares how the team’s rigorous approach to design implementation and methodology were critical factors in achieving first-time silicon success for a major networking customer.

Designing complex ASICs and delivering them on time is no easy task. It requires a powerful combination of design expertise, proven methodologies, and robust process technology.

One year ago, with the launch of GF’ first ASIC platform, FX-14®, we gained competitive ground with a new pipeline of ASIC offerings on our 14nm FinFET process technology (14LPP). Since then, we have combined a rich legacy of ASIC expertise from our acquisition of IBM Microelectronics with manufacturing scale and improved access to IP and design tools to enable a new generation of customers to easily adapt their chip designs to the FX-14 offering.

GF has decades of high-speed interconnect, memory, processor, and packaging innovation

Today, I am pleased to share an exciting milestone in our journey: We have achieved first-time-right silicon success for a lead product using our FX-14™ ASIC platform, with a major networking customer (to remain anonymous) bringing up a board in one week and declaring a fully functional ASIC chip.

Such an aggressive schedule would be impressive for any product, but this is no ordinary chip—the highly complex design incorporated a high-performance ARM® 64-Bit core, a DDR memory subsystem including DDR memory controllers and PHYs, multiple high-speed backplane SerDes covering a broad range of interface standards, dense 1- and 2-port SRAMs, high-frequency I/Os, and PLLs.

How did we accomplish this? A key factor in our approach is the use of an integrated test chip based methodology to rigorously vet our design implementation and methodology well in advance of customer product tapeout. Our ASIC design-for-test features include full scan, IEEE 1149.1 and 1149.6 JTAG boundary scans, and complex IP that meets the IEEE 1687 standard. Additionally, we use a three-phase netlist signoff process with stringent entrance and exit milestone requirements. This type of ASIC platform rigor before product tapeout is essential to enabling first-time customer success.

Another key contributor was the maturity of the 14LPP manufacturing technology at our Fab 8 facility in upstate New York, which is in high-volume production on multiple products. By leveraging the FX-14 design platform, the team was able to turn around defect-free parts quickly in order to guarantee first-time-right silicon, while also achieving a power reduction of more than 50 percent over the customer’s previous design.

Achieving first-time-right silicon success and fast board bringup for such a complex chip demonstrates the power of GF’ ASIC FX-14 design system. This, along with our proven expertise and design methodology, helps ensure that our customers can design with confidence and achieve a fast path to volume production.

Today, we have many customer designs underway in FX-14 across a number of segments, including wired networking, wireless base station, compute, storage, and aerospace and defense applications. We are committed to partnering with these and other customers to help them bring their most complex designs to market.

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