“There are far fewer bigots out there than there were two years ago.” Dan Hutcheson, CEO of VLSI Research
Two years ago, when Dan Hutcheson, CEO of market research firm VLSI Research Inc. (Santa Clara, Calif.), set out to interview influential IC and intellectual property managers about fully depleted silicon on insulator (FD-SOI), he found two top-of-mind concerns: the availability of external IP which design teams could combine with internal intellectual property, and the then-lack of a process technology roadmap.
Hutcheson redid the VLSI Research survey this year and found a different landscape: the 2018 survey respondents were much less concerned with the roadmap issue now that GLOBALFOUNDRIES has committed to a 12nm node for its FDX technology, and “IP is much less of an issue,” Hutcheson said during a presentation of the 2018 survey results at the 2018 SOI Silicon Valley Symposium in late April.
Hutcheson asked 24 people—decision-makers at companies accounting for more than half of the IC and intellectual property markets—about the transistor reasons to design with FD-SOI. Nearly 40 percent cited “better gain for analog” as the top reason, with a similar number citing lower leakage and better parasitics. Lower noise, better transistor matching, thermal properties, reliability concerns, and better radiation protection followed in importance.
The 2018 survey participants are now aware that RF and mixed-signal technologies are more readily implemented in FD-SOI, including a widely held view that FD-SOI is a better solution for 5G and millimeter-wave RF SoCs.
Times Have Changed
When the 2016 survey was conducted, finFET-based processes were just becoming available. At that time people were thinking in either-or mode: either finFETs or FD-SOI, one or the other. Now that finFETs have become widely available, more nuanced thinking is taking hold. “Now, most people have said finFETs and FD-SOI are complementary technologies, and which one you use depends on application needs,” Hutcheson said.
FinFET-based technologies offer higher performance, integration, and density. However, the design and mask costs are higher than FD-SOI, even though finFET costs have come down over the last two years due to depreciation of tool sets.
Many of the survey respondents said the primary advantages of FD-SOI centered on RF, or “high-mix SoCs” with analog, digital, and RF on the same die. In product markets where RF and sensor integration are valuable, FD-SOI is seen as the way to go “much more than before,” he said.
The respondents told Hutcheson that the fully depleted planar transistors on SOI offer “better gain for analog, better matching, and they are much easier to match. The automotive guys see a better thermal range, and more stable operation” in automotive environments. Also, analog designs benefit from the better gain possible with the FD-SOI depletion-mode transistors, compared with the enhancement-mode transistors of finFETs.
“FD-SOI is uniquely positioned for 5G because of the better parasitics. Some people are trying to use fins for 5G, but fin parasitics are a deciding factor. To paraphrase the respondents, ‘You can always find a way to engineer around anything. But the question is: How much do you want to pay to engineer around that?’” he said.
The 2018 survey asked for the top reasons to favor finFETs. The largest reasons were the performance and density advantages held by leading-edge finFETs. Nearly 30 percent said “FD is not cost-effective on a structural basis in these domains.” About 15 percent of the respondents said they believe millimeter-wave ICs are “possible to do with bulk.” Others cited a wide variety of reasons for preferring finFETs, including challenges in designing with back-biasing, the finFET ecosystem “has no peers,” a lack of FD-SOI IP, and “management says no.”
“I asked about body-biasing and found people who said it was oversold,” Hutcheson said. One person said “if I go to my boss and say, we ought to do this because we want to do body-biasing, he is likely to say it is too complex and risky, so just do bulk. It’s better to first sell them on FD’s unique transistor features to management first and then add body-biasing as a bonus later.”
The respondents said FD-SOI had business-reason attractiveness, with about 30 percent citing lower design costs as the top business reason to design with FD-SOI. Lower manufacturing costs, fewer masks, and faster cycle-times/ time-to-market followed.
Hutcheson noted that the Internet of Things label encompasses several large market segments. For edge IoT markets where power consumption is important—which he referred to as “clever power with on/off mission profiles” —FD-SOI “has a huge advantage.” And, he said the survey indicated FD-SOI has advantages for markets where the product life is short, and for companies that have ”low budgets for chip design.”
The main takeaway from the 2018 survey is that managers and engineers are more willing to consider FD-SOI as a complement to finFETs, or in some cases as the only process roadmap that fits their company’s product requirements. Fully 75 percent of the survey respondents said they would consider running two roadmaps, one for finFETs and another for FD-SOI.
“Two years ago, people had a dramatic take on the question: is it finFETs? Or is it FD-SOI? At that time it was an OR-gate kind of situation, but now it is more like an AND gate. People are willing to use both. There are far fewer bigots out there than there were two years ago,” he said.