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Foundry Files

Executive Perspective: The Big Shrink

When we in the semiconductor industry talk about shrinking, most of the time we mean device scaling. But another type of shrinking is taking place, too, and I want to talk about its implications for the industry.

I’m referring to the shrinking number of companies at the top of the market, resulting from the continuing consolidation of fabless companies. Since the beginning of 2014, mergers and acquisitions valued at more than $150 billion have taken place in our industry, nearly 10 times the yearly average. These have been driven by a combination of low interest rates, saturation in the mobility space, slowing growth rates and an overall squeeze on profitability


This wave of corporate tie-ups is leaving a huge amount of disruption in its wake for foundries and foundry customers alike, as newly integrated companies seek to exercise their larger-scale purchasing power, consolidate their supply chains, simplify their roadmaps and drive a multitude of new integration synergies.

Disruption is also occurring because of new architectures and more complex packaging technologies, which are making it harder to distinguish where wafer processing ends and packaging begins.

As a result, we are seeing a growing trend by system houses to engage directly with foundries for complete turnkey solutions, from fab to test to packaging to finished goods inventory – these may even involve design centers along with the complete supply chain.

Foundries face a number of critical requirements and challenges as a result of these trends. One is that large-scale foundry operations are more important than ever, as the largest customers simplify their supply chains and ask their foundry partners to do more. The fact that margins are under great pressure also drives the need for scale, and for continuing cost reductions.

Moreover, decision-making has become a higher-stakes process than ever before as a result of the fewer number of customers and foundries at the leading edge.


GLOBALFOUNDRIES is pursuing a multi-faceted approach to meet these challenges. With regard to scale, we are building the capability in our Dresden fab for hundreds of thousands of 22FDX® FD-SOI wafer starts annually, in a facility that has the ultimate capacity for more than a million wafer starts a year overall.

Also, the acquisition of IBM’s semiconductor operations has given us more capacity, and more supply for customers. With the two additional fabs – one in Burlington, Vermont and the other in East Fishkill, New York – we can expand our capacity in RF SOI as well as other processes. And, on the ASIC side we have a very strong 14nm ASIC business and IP portfolio, which directly connects our foundry to end-market system houses.

Meanwhile, in collaboration with select design partners, equipment and material suppliers and OSAT partners, our offerings span the range of design-fab-turnkey solutions. And I’m proud to say there is no better example of our end-market expertise – that is, our ability to engage architects – than our work to ensure that viable, cost-effective solutions exist for the forthcoming move to 5G cellular networks.

In the end, the industry is changing so swiftly and deeply that nobody can be certain how it will evolve. But one thing is for certain: We at GF are planning and implementing solutions that address as broad a swath of our customers’ current and future requirements as needed, regardless of how things may evolve.

About Author

Gregg Bartlett

Gregg Bartlett is head of the GLOBALFOUNDRIES CMOS Platforms Business Unit, responsible for management of the company’s leading-edge and mainstream products, not including ASIC and RF.

Bartlett joined GF in 2009 and has served in various senior executive roles including chief technology officer and head of technology development, product management, and strategy and corporate development.

Prior to joining GF, Bartlett had a 25-year career in technical and management positions at Freescale Semiconductor and its predecessor, Motorola's Semiconductor Products Sector. Bartlett served as vice president of design technology at Freescale, responsible for design methodology and the creation of design collateral for advanced solutions across networking, automotive, wireless and analog product markets. His tenure emphasized collaborative R&D efforts, including executive representation of Freescale in the Crolles 2 Alliance in Europe.

Bartlett has served as a member of the board of directors of the Semiconductor Research Corporation and Executive Committee, as well as various consortia governance committees. He holds a bachelor's degree in chemical engineering from Kansas State University.

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