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Foundry Files Blog

Choices Aplenty at the 7 nm Node

  • By: Dave Lammers
  • February 15, 2017
  • Category: Uncategorized

When I asked Gary Patton about the 7nm logic node, shortly after he started his new job as CTO, he emphasized two points. First was execution, and to that end Patton had implemented a tighter operations framework, with milestones designed to get the 7nm platform to customers on time.

Second was performance. Patton spoke at length about the need for performance gains, and how GLOBALFOUNDRIES had been strengthened by the influx of several hundred IBM technologists. “The IBM technology development team was all about delivering performance,” Patton said, promising that the GF 7nm technology would lead the foundry industry.

More recently, I spoke with D.K. Sohn, vice president of Advanced Technology Development, who leads the 7nm effort at Fab 8 in Malta, N.Y. Sohn, who spent two years leading 14nm development at GF, highlighted three challenges at the 7nm FinFET node for boosting of device performance. The first, which Sohn called the “foundation of performance boosting,” is how the fin is shaped, how the contacts are engineered to reduce resistance, and lower-k module process design.

[Source: GLOBALFOUNDRIES] Innovative device technology for 7nm FinFET, guided by detailed analytical work and learning from prior technologies.

While some in the industry have talked about taller fins, Sohn said “we plan to keep our fin design to balance between DC gain and AC loss due to parasitic capacitance. We have gained experience, through the 14nm volume product ramp up, in creating the fin module and downstream process control issues.

A second challenge is stress engineering, where Sohn said “there are still opportunities” to improve carrier mobilities. However, as the transistor area shrinks, there is less room “from a volume perspective” to add more germanium as the PMOS stressor.

One possibility – still under study for a 7nm or beyond offering – is to move to a silicon-germanium (SiGe) channel in the fin of the PMOS transistor. Sohn said “for the PMOS, we have been studying the SiGe Fin, and progress is very good. We have seen multiple confirmations, using a test mask set. So we are still thinking about it – that would be another way to differentiate for performance.”

The debate is equally interesting on the NMOS side, where there is little or no room for the nitride stressors that some companies have employed. One possibility is to add a stress-relaxation buffer (SRB) layer, under development within the IBM Alliance at Albany, N.Y. and elsewhere.

Sohn said bringing in an SRB for the NFET, or a SiGe channel for the PFET, are among “the next round of performance boosters we can pull in. Absolutely, these are examples of how our research collaboration with IBM, and strengthening our internal execution engine, have been very helpful.

For the 7nm transition, the most widely discussed industry-wide topic has been when EUV lithography will be ready for prime time. One foundry has said it plans to rely on EUV from the get-go, while another has said it will bring in EUV at a later stage of the 7nm generation after using multiple patterning for risk production.

Mike Chen, 7nm product line manager at GF, said the EUV platform has made significant progress, and GF is preparing an EUV volume manufacturing infrastructure at Fab 8 in Malta, N.Y. to respond to industry demand. “We will be able to assess the process maturity of EUV versus the cost and cycle time reduction, in 2018,” Chen said.

The goal all along has been to make the choice of patterning “transparent” to the customers, Chen said. For high-volume designs that will move to EUV after initial runs using multi-patterning (MP), “customers will be able to convert, so that it doesn’t require (design-tool-level) coloring anymore.

Once EUV is manufacturing-ready, patterning becomes simpler, making it “conceivable to make it (a conversion from optical MP to EUV single layer print) transparent to the customer.” Going the other way, from a non-colored single exposure process to a multiple patterning scheme, is a more-difficult transition. And because the EDA industry has developed design tools for multi-patterning at previous nodes, using MP at 7nm is not a major burden on design teams.

Fin creation and the interconnect layers in the middle end of the line (MEL) that require multi-patterning are the layers most suited to a conversion perspective. Customers have invested in developing their products, and they can’t wait for EUV to come on line.

Moving to EUV will simplify the manufacturing process, reducing cycle times in the fab. “In the early years of EUV it is less about cost reduction and more about eliminating multiple patterning steps and reducing the cycle time. Our initial product offering, our 7nm launch, is not dependent on EUV. But our view is that when EUV becomes ready it will be ready within the life of 7nm,” Chen said.

[Source: GLOBALFOUNDRIES] GF’s portfolio scales across both 2.5D as well as 3D packaging solutions

Interconnects are also gaining more attention as design rules shrink, for the fundamental reason that resistance increases as metal lines narrow. Because of the relatively thick liners required for tungsten connections from the transistor into the back end, or MEL, has developed into a performance-limiting area.

Chen said “resistance and capacitance are both going in the wrong direction as we scale. We believe if we continue to use traditional interconnect materials (tungsten), more drive current would be left in the transistor that cannot get out. It would be wasted by parasitics in MEL, which is becoming a dominating component, and historically that has not been the case.

One likely solution is to bring in a cobalt (Co)-based MEL interconnect, where the liner thickness can be reduced significantly. Rohit Pal, the deputy director of technology development who heads up the process integration team at Fab 8, said the reduced liner thickness would permit an increased volume of material, compared with tungsten. And cobalt has 50 percent less resistivity.

Sohn said the semiconductor industry has a lot of experience with cobalt due to its use in silicides, including cleaning techniques. But bringing it in to the 7nm node is still under consideration. We decided this is the process direction, but there still are implications for tuning the integration scheme, he said.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF's Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

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